The development and manufacturing of electronic products is continually being challenged by a growing market demand for smaller, more efficient, and a higher performance product. The current trend toward miniaturization is driven to a large extent by portable electronic product applications. However, other product categories are under pressure to reduce size as well, such as in the medical device industry where reliability also must be assured. There are numerous packaging techniques that have been used in the past. For example, some of such techniques include dual in-line packaging (DIP), leadless chip carrier processing, leaded molded plastic packaging, surface mount processing, etc.
In addition, more recently, chip scale packaging (CSP) has been introduced. Generally, CSP includes the packaging of integrated circuits in packages which are slightly larger than the integrated circuits being packaged. Ceramic chip scale packaging (CCSP) includes the use of ceramic substrates in such chip scale packaging of die.
Such conventionally available packaging processes are generally inadequate for packaging many devices, e.g., such currently available packages do not provide adequate characteristics or functionality when used to package high voltage dies. For example, many of the packages conventionally available, such as DIP packages, do not provide surface mount capabilities and are in general much larger than the die being packaged.
High voltage dies have been traditionally packaged in leadless chip carriers and large leaded molded plastic packages (e.g., TO220, SOT23, etc.). Although other packaging options are available (e.g., micro surface mount technology), such packaging options require additional wafer level processing to implement, such as metal passivation and deposition steps, plasma etch steps, etc. Further, many of such packaging options will not work with a high voltage die because in many circumstances, back side or bottom surface contact for such a die (e.g., a field effect transistor die) is not available, the deposited metal is generally too thin too handle current requirements of such high voltage components, such packages cannot withstand the voltage stress levels presented, etc.
Table 1 below lists U.S. Patents that describe a couple of packaging options:
TABLE 1 ______________________________________ U.S. Pat. No. Inventor(s) Issue Date ______________________________________ 4,681,656 Byrum 21 July 1987 5,528,135 Kawamura et al. 18 June 1996 ______________________________________
All patents listed in Table 1, and elsewhere herein, are hereby incorporated by reference in their respective entirety. As those of ordinary skill in the art will appreciate readily upon reading the Summary of the Invention, Detailed Description of the Embodiments, and claims set forth below, many of the devices and methods disclosed in the patents of Table 1 may be modified advantageously by using the teachings of the present invention.